1. Field of the Invention
The present invention relates to peak voltage detectors, and more particularly, to peak detectors wherein high accuracy and minimum susceptibility to noise are desired.
2. Description of the Related Art
FIG. 1 shows a typical prior art peak voltage detector 10 which consists of a comparator 11, a charge pump 12 and a hold capacitor C.sub.h. When V.sub.in is greater than V.sub.out, the noninverting output of the comparator will be high and the inverting output will be low. This turns transistor Q1 off and transistor Q2 on. Current I1 thus flows through transistors M1 and Q2, with the current in transistor M1 being mirrored by transistor M2 as current I.sub.ch. While transistor Q2 is on, I.sub.ch flows into capacitor C.sub.h to charge C.sub.h. When V.sub.in is less than V.sub.out, the inverting output of the comparator will be high and the noninverting output will be low. Transistor Q1 is now on and transistor Q2 is off. Now current I1 will flow directly from V.sub.cc through transistor Q1. The current in transistor Q2 and thus the current I.sub.ch will be zero, and capacitor C.sub.h will hold the previous voltage.
FIG. 2 shows the voltage and current waveforms for the circuit of FIG. 1. One of the disadvantages of the prior art described above is that the output voltage V.sub.out is almost always higher than the actual peak value of V.sub.in. This is because comparator 11 cannot respond instantaneously to its inputs. As a result, even after V.sub.out becomes greater than V.sub.in, I.sub.ch stays on for a finite time delay (d), as shown in FIG. 2. During the finite time delay (d), capacitor C.sub.h continues to be charged. This results in an error voltage V.sub.e1. The amount of overshoot represented by V.sub.e1 depends on the magnitude of I1, the delay d and the size of capacitor C.sub.h.
Another disadvantage of the prior art is that the topology shown in FIG. 1 is highly susceptible to noise spikes occurring near the peaks of V.sub.in after the true peak has been captured by capacitor C.sub.h. FIG. 3 presents the voltage waveform of V.sub.in with a voltage spike V.sub.spike occurring near the peak of V.sub.in and the voltage waveform of V.sub.out. FIG. 3 also shows the resulting current pulse 26 developed in I.sub.ch due to the voltage spike V.sub.spike. Current pulse 26 further charges capacitor C.sub.h and creates an error voltage V.sub.e2 in the output voltage V.sub.out.
To overcome the drawbacks of the prior art described above, the present invention provides a current reduction circuit and a small leakage current to reduce the amount of error in the output voltage occurring due to the noise spikes in the input voltage and the characteristics of a non-ideal comparator.